演講摘要：
Electrostatic discharge (ESD), Latch-up (LUP), Electrical over stress (EOS), and Time-dependent dielectric breakdown (TDDB) are well-studied reliability issues. ESD/LUP/EOS are often studied at the transistor/gate level, while interconnect TDDB is often studied from breakdown model & metal-dielectric material composition point of view. However, the complexity of their effects is expanding beyond a single device/gate, resided deep inside a chip, and increasing with the advance of technology. Applying dynamic simulation on a large design to yield reliable outcomes has not been promising so far, due to the enormous amount of data to be processed and the uncertain simulation inputs. Here,I am presenting a static approach and design automation methodology to assist and enhance rule-based design reliability verification for full chip assembly.