IC實體層佈局的低功耗設計 Low power design in IC physical implementation
演講摘要:
節省功耗一直是工程上的挑戰,這不僅只是在可攜式裝置,在工程方面,也需要有較佳的能源消耗率來提升產品競爭力。幫助工程人員了解低功耗佈局方法,可運用這些概念在專案上且大部份技巧皆可被使用在現有的製程上。
It is challenging to save power in today’s design, not only for cell phone or portable devices, in engineering, also need to have good energy efficiency to enhance product competitive-ness. The goal of this presentation is to help IC designer un-derstand the low-power implementation method, these con-cepts can guide IC designer how to choice low-power in their project and most of techniques are used for almost all pro-cess nodes.

場次:
6
演講日期:
2019-10-18
主講人:
蔡志鴻 經理
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